PURPOSE: To obtain a demodulated signal which has less errors in demodulation due to timing jitters by extracting a reproduced clock required for the demodulation by using a high-frequency clock whose frequency is set to a multiple of an original signal bit frequency and a reproduced MFM-modulated signal.
CONSTITUTION: A reproduced MFM-modulated signal is inputted to an edge extracting circuit 20 to obtain a pulse, which rises and falls correspondingly, by a high-frequency clock having a period of one Nth (N≥1) of the bit period TO of an original signal. A counter circuit 23 obtains a reproduced clock which follows up the MFM modulated signal by the output of a preset-value generating circuit 24 passed through a counter circuit 21 for a "101" detection gate and a gate circuit 22. The output of a TO/2 delay counter 25 is inverted and inputted to a flip-flop 28 to obtain a demodulated signal by using the reproduced clock inputted to a clock terminal. Thus, the demodulation signal which has less errors in demodulation due to jitters is obtained.
MATSUSHIMA KOUJI
TSUJI SHIROU
SHIMEKI TAIJI
KIHARA NOBUYOSHI
| JPS5037414A | 1975-04-08 | |||
| JPS547246A | 1979-01-19 | |||
| JPS54151014A | 1979-11-27 |