Title:
DESCRAMBLE METHOD, SCREAMBLE PATTERN GENERATING CIRCUIT AND DISK DEVICE
Document Type and Number:
Japanese Patent JP3566007
Kind Code:
B2
Abstract:
PROBLEM TO BE SOLVED: To speed scramble pattern generation, to improve the transfer rate of data and to speed data processing.
SOLUTION: A selector 25 of a scramble pattern generating circuit 21 inputs the initial value α of the scramble pattern and bits, b14' to b0', of the generated scramble pattern. The selector 25 selects either of the initial value α or the generated scramble pattern based on the selection signal SL. DFF 26A-26O latch the bits, b14-b0, outputted from the selector 25 based on a clock CK. The output data of DFF 26H-26O are outputted as scramble values SK. The output data of DFF 26I-26O is outputted as bits: b14', b13', b12', b11', b10', b9', b8'. The EOR circuit 27A-27H of a logic circuit 25 outputs bits, b7'-b0'.
Inventors:
Masashi Yamawaki
Application Number:
JP30064596A
Publication Date:
September 15, 2004
Filing Date:
November 12, 1996
Export Citation:
Assignee:
富士通株式会社
富士通ヴィエルエスアイ株式会社
富士通ヴィエルエスアイ株式会社
International Classes:
G06F3/06; G06F11/10; G11B20/10; G11B20/12; H04L25/03; (IPC1-7): G11B20/10
Domestic Patent References:
| JP5063697A | ||||
| JP6169305A | ||||
| JP6141004A | ||||
| JP6046419A | ||||
| JP7297982A | ||||
| JP10013407A | ||||
| JP10079716A | ||||
| JP2093835U |
Attorney, Agent or Firm:
Hironobu Onda