Title:
【発明の名称】アナログ逆伝搬学習回路
Document Type and Number:
Japanese Patent JP3110434
Kind Code:
B2
Abstract:
PURPOSE:To shorten the learning time and to simplify the constitution of an analog reverse transmission circuit by using the hardware which work in parallel with each other between neurons and at the same time multiplexing an inter- layer wiring in time division. CONSTITUTION:A pre-layer neuron unit 1 is provided together with an analog switch 2 which changes over the output of the unit 1, a multiplier 3, an analog switch 4, an electrochemical integration element 5 serving as a weight coefficient storage element which is changed over by the switch 4, an integrator 6, and a sigmoid function generating circuit 7. These hardware working in parallel with each other between the neurons transmit the analog voltage in a time division multiplexing system to perform the adverse transmission learning. As a result, the learning time is shortened and the constitution is simplified for an analog reverse transmission learning circuit.
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Inventors:
Toyosaka Moriizumi
Takamichi Nakamoto
Takamichi Nakamoto
Application Number:
JP6769590A
Publication Date:
November 20, 2000
Filing Date:
March 17, 1990
Export Citation:
Assignee:
Japan Science and Technology Agency
International Classes:
G06G7/60; G06F15/18; G06N3/04; G06N99/00; (IPC1-7): G06G7/60; G06F15/18
Domestic Patent References:
| JP264787A | ||||
| JP264788A | ||||
| JP266688A |
Attorney, Agent or Firm:
Mamoru Shimizu