Title:
【発明の名称】集積デジタルアナログ変換器のための組込み式自己テスト
Document Type and Number:
Japanese Patent JP2003512755
Kind Code:
A
Abstract:
A circuit arrangement and method for testing the differential non-linearity (DNL) of a digital-to-analog converter (DAC) determines whether the digital-to-analog converter has an analog output that is monotonic, and thus the DAC is functional The design is appropriate for being implemented on an integrated circuit containing a digital-to-analog converter, creating an efficient self-test circuit arrangement. A counter generates a monotonic sequence of digital input codes for a digital input of the digital-to-analog converter. A monotonicity comparator, such as a one-stage or multistage sample and hold circuit arrangement, detects any non-monotonic transition in the analog output of the digital-to-analog converter, generating an error signal as an output. An output switch, such as a digital flip-flop, may be set by the error signal, for monitoring by other devices. A clock signal synchronizes the counter and the monotonicity comparator. A reset signal may be included to reset the counter to the first digital input code in the sequence, The reset may also reset the output switch.
Inventors:
Michel Jean Yeves
Application Number:
JP2001531209A
Publication Date:
April 02, 2003
Filing Date:
August 28, 2000
Export Citation:
Assignee:
Konin Krekka Philips Electronics NV
International Classes:
G01R31/28; H03M1/10; G01R31/316; (IPC1-7): H03M1/10; G01R31/28; G01R31/316
Attorney, Agent or Firm:
Masao Sawada