Title:
【発明の名称】集積回路及び半導体装置
Document Type and Number:
Japanese Patent JP2752109
Kind Code:
B2
Abstract:
PURPOSE:To extend the circuit to an arbitrary number of layers and an arbitrary scale by arraying and constituting a synapse block and a neurone block in the multilayer perceptron circuit device with prescribed regularity. CONSTITUTION:A synapse block 1 for executing a load operation is provided with (n) X (m) pieces of plural synapses 2, a first wiring 3 constituted of (n) pieces of signal lines arrayed in the same direction, and a second wiring 4 constituted of (m) pieces of signal lines, and each synapse 2 inputs a signal from a first wiring 3, executes a load operation with a prescribed weight coefficient and outputs its result to a second wiring 4. Also, a neurone block 5 performs a prescribed conversion to a signal inputted from its outside, and outputs its result to the synapse block 1 through a first wiring 3. In such a way, by placing plural pieces of unit synapse blocks and unit neurone blocks which are realized as integrated circuits, respectively, a perceptron circuit of an arbitrary scale can be realized.
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Inventors:
SHIMA TAKESHI
Application Number:
JP28669388A
Publication Date:
May 18, 1998
Filing Date:
November 15, 1988
Export Citation:
Assignee:
TOSHIBA KK
International Classes:
G06F15/18; G06N3/04; G06N3/063; G06N99/00; G06G7/60; G06T7/00; H01L21/822; H01L27/04; (IPC1-7): G06G7/60; G06F15/18; H01L21/822; H01L27/04
Domestic Patent References:
| JP63124162A | ||||
| JP62262172A |
Attorney, Agent or Firm:
Yasuo Miyoshi (1 outside)