Title:
HIGH-QUALITY, HIGH-VOLTAG VERTICAL TRANSISTOR AND PREPARATION THEREOF
Document Type and Number:
Japanese Patent JPH077149
Kind Code:
A
Abstract:
PURPOSE: To provide a transistor device having a low ON-state resistance value, a high interrupt voltage, and a minimum transistor area region. CONSTITUTION: An epitaxial layer 14 is formed on a semiconductor substrate layer, a base layer 16 is formed on the epitaxial layer 14, and a source layer 18 is formed on the base layer 16. A trench region 22 is formed so as to be extended through the source layer 18, the base layer 16, and the epitaxial layer 14 to a semiconductor substrate layer. An oxide layer is formed on the source layer 18 and the inside wall of the trench region 22, so that the width of the oxide layer can be made larger at the bottom part of the trench region 22 than that at the top part, such that an added high voltage can be held. A gate layer is formed in the trench region on the oxide layer. A gate layer 26 completely turns a drift region formed in the epitaxial layer 14 into a deficient state under the highest-rated stopping state. Thus, the drift region components of an ON-state resistance value which is a dominant parameter in a device with a very high voltage can be decreased.
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Inventors:
SATSUTOUINDAA MARUHI
Application Number:
JP5294A
Publication Date:
January 10, 1995
Filing Date:
January 04, 1994
Export Citation:
Assignee:
TEXAS INSTRUMENTS INC
International Classes:
H01L21/331; H01L21/336; H01L29/739; H01L29/78; H01L29/423; (IPC1-7): H01L29/78
Attorney, Agent or Firm:
Akira Asamura (3 outside)
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