【発明の名称】電圧制御発振回路

Japanese Patent JP2531742

B2

A voltage controlled oscillator circuit comprises a phase-locked loop section (1) which includes a first delay circuit (3, 5), having cascade-connected m-stage delay sections whose delay times are controlled by a control signal (PV), for delaying a reference frequency signal (Fref) by an optional period or by a prescribed period, a phase difference voltage generating circuit (4, 6, 7) for generating a phase difference voltage (Voff) representing a phase difference between the output (NDo) of the first delay circuit (3, 5) and the reference frequency signal (Fref), and a first control signal generating circuit (8) for generating the control signal (PV) for determining the signal delay times of the respective delay sections of the first delay circuit (3, 5) based on a reference voltage (Vref) and the phase difference voltage (Voff), and a voltage controlled oscillator section (2) which includes a second delay circuit (10, 11), including cascade-connected n-stage delay sections having structures equivalent to those of the delay sections of the first delay circuit (3, 5), wherein an output of the second delay circuit (10, 11) is fed back to the input terminal thereof so that a ring oscillator circuit is constituted, and a second control signal generating circuit (9) for generating a control signal (PV) for determining the signal delay times of the respective delay sections of the second delay circuit (10, 11) based on the phase difference voltage (Voff) and a control voltage (Vcont) for controlling the output frequency.

MUROGA HIROKI
MOGI HIROYUKI
SUZUKI SATOSHI

JP11970188A

September 04, 1996

May 17, 1988

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TOSHIBA KK
TOSHIBA MAIKUROEREKUTORONIKUSU KK

H03L7/18; H03K3/03; H03K3/354; H03K7/06; H03L7/081; H03L7/099; (IPC1-7): H03L7/099; H03K3/354

JP5555621A
JP61107810A
JP61214615A
JP5537031A

Takehiko Suzue (2 outside)

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