Title:
【発明の名称】電流メモリ及び電流メモリを有する回路装置
Document Type and Number:
Japanese Patent JP2000515293
Kind Code:
A
Abstract:
A current memory cell comprises a fine MOS memory transistor (T1) and a coarse MOS memory transistor (T2) connected in series between two power supply rails. Such current memory cells are preferably designed so that the sum of the voltage drops across the coarse and fine memory transistors when diode connected is equal to the supply voltage. In order to achieve this while leaving flexibility in choosing the transistor saturation voltages an auxiliary power rail (Vdda) is generated using as a reference the voltage drops across two diode connected transistors (T6, T7) which conduct a current equal to the bias current in the current memory cell (3).
Inventors:
Hooges John Barry
Application Number:
JP52933098A
Publication Date:
November 14, 2000
Filing Date:
March 12, 1998
Export Citation:
Assignee:
Konin Krekka Philips Electronics NV
International Classes:
G06G7/184; G06G7/12; G11C27/02; (IPC1-7): G11C27/02; G06G7/184
Attorney, Agent or Firm:
Susumu Tsugaru