PURPOSE: To prevent slip from being generated at the time of conversion by starting the operation of a fixed cycle circuit with the output of a differentiation circuit and supplying a signal in a fixed cycle to a serial conversion circuit only with a clock for serial data later while suppressing the output of the differentiation circuit.
CONSTITUTION: FF 21 and 22 of a differentiation circuit 2 and an AND circuit 24 input clocks (Pc and Sc) for parallel and serial data, and an FF 23 shifts a pulse obtained by differentiating the Pc with the Sc by applying delay. Therefore, a signal setting the pulse near the center of a parallel signal is counted by a fixed cycle circuit 3 while using a quatenary counter 33, and a synchronizing load signal in the fixed cycle is generated and supplied to a serial conversion circuit 1. At such a time, since the Pc and the Sc are asynchronous, outputs Q0 and Q1 of the counter 33 are ORed by an OR circuit 34 and impressed to the inverted input of an AND circuit 31, and the differentiated output is suppressed. On the other hand, before the first differentiated signal pulse to load the counter is inputted, an output stop circuit 4 stops the output of the synchronizing load signal. Thus, the slip of the circuit 1 can be prevented from being generated.
| JPS5952914 | DEMULTIPLEXER |
| JP3986358 | Serial / parallel converter and semiconductor device |
KIKUCHI HIROAKI
KATO TSUGIO
