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Title:
DETECTING SYSTEM FOR CPU RUNAWAY
Document Type and Number:
Japanese Patent JPH0225937
Kind Code:
A
Abstract:

PURPOSE: To omit the intrusion of noises into a bus line set between a ROM and a parity calculating part and to surely detect the CPU runaway by comparing a total parity given from the parity calculating part and a parity produced internally by a CPU to detect the runaway.

CONSTITUTION: A parity calculating part 12 is prepared to a chip forming a ROM 11 to output a parity after totalizing the number of '1' of an input address given to the ROM 11 and the number of '1' of the output data. Furthermore an address bus 13 and a data bus 14 which connect the part 12 and the ROM 11 are also set on the same chip as these part 12 and ROM 11. As a result, both buses 13 and 14 are shortened and at the same time no noise intrudes into both buses at all. Thus the CPU runaway can be surely detected even though the noises intrudes into the buses set between the part 12 and the ROM 11.


Inventors:
YAMAGUCHI MASAHIKO
Application Number:
JP17630988A
Publication Date:
January 29, 1990
Filing Date:
July 14, 1988
Export Citation:
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Assignee:
FUJITSU DENSO
International Classes:
G06F11/10; G06F11/30; (IPC1-7): G06F11/10; G06F11/30
Domestic Patent References:
JPS5637899A1981-04-11
JP54062633B
Attorney, Agent or Firm:
Furuya



 
Next Patent: JPH0225938