Title:
DEVICE FOR GENERATING BIAS CURRENT
Document Type and Number:
Japanese Patent JPH07226636
Kind Code:
A
Abstract:
PURPOSE: To provide a bias current generation device which requires minimum connection lines with low noise. CONSTITUTION: For a differential pair constituted of transistors 16 and 18, reference voltage Ur is applied to the gates of the transistors through input terminal 10 and 12. The sources of the transistors are connected to a current mirror circuit 40 constituted of transistors 42 and 46. The drains of the transistors are connected to a current mirror circuit 22 constituted of transistors 26 and 30. The sources of the transistors 16 and 30 are connected in common and a node 24 is connected to a current mirror circuit 32 constituted of transistors 34 and 36. The sources of the transistors 36 and 42 are connected in common.
Inventors:
KURAASU BURUTO
GODEFURIDASU YOHANESU HERUTORU
GODEFURIDASU YOHANESU HERUTORU
Application Number:
JP651395A
Publication Date:
August 22, 1995
Filing Date:
January 19, 1995
Export Citation:
Assignee:
PHILIPS ELECTRONICS NV
International Classes:
G05F3/24; G05F3/26; H03F3/343; H03M1/74; (IPC1-7): H03F3/343; H03M1/74
Attorney, Agent or Firm:
Akihide Sugimura (5 outside)
Previous Patent: Antiviral article and antiviral resin composition
Next Patent: LOGARITHMIC AMPLIFIER AND AMPLIFICATION METHOD
Next Patent: LOGARITHMIC AMPLIFIER AND AMPLIFICATION METHOD