Title:
DEVICE AND METHOD FOR DETECTING MEMORY REWRITE OPERATION ERROR
Document Type and Number:
Japanese Patent JP3190867
Kind Code:
B2
Abstract:
PROBLEM TO BE SOLVED: To shorten the rewrite time by providing a means such as a rewrite means rewriting an inspection bit output corrected by an inspection bit error correction means to a storage element without through an error correction/ detection circuit.
SOLUTION: When data and the inspection bit, which are corrected by error correction circuits 6 and 7, a supplied and stored to/in a read data storage register 202, a selector 3 selects output data of the read data storage register 202 and supplies it to a write data storage register 102. The write data storage register 102 stores output data of the selector 3 and outputs write data and the inspection bit to the memory array 4 at a prescribed timing. Thus, an ECG circuit 2 generating the inspection bit can be bypassed at the time of rewriting by newly providing the error correction circuit 7 to the inspection bit added to read data. Thus, rewriting time can be shortened.
Inventors:
Tsuyoshi Kisumino
Application Number:
JP33391797A
Publication Date:
July 23, 2001
Filing Date:
December 04, 1997
Export Citation:
Assignee:
Kofu NEC Corporation
International Classes:
G06F11/10; G06F12/16; (IPC1-7): G06F11/10; G06F12/16
Domestic Patent References:
| JP6339061A | ||||
| JP63298457A | ||||
| JP6232825B2 | ||||
| JP5645240B2 |
Attorney, Agent or Firm:
Yoshiyuki Iwasa