Title:
DEVICE AND METHOD FOR GENERATING CIRCUIT EMULATION CLOCK
Document Type and Number:
Japanese Patent JP3522213
Kind Code:
B2
Abstract:
PROBLEM TO BE SOLVED: To provide a device and a method for circuit emulation clock generation which make it possible to adjust the optimum buffer storage depth when data transmission delay is reduced by an adaptive block method and also make it possible to adjust buffer storage depth even in operation by providing a protection buffer for underflow prevention.
SOLUTION: A buffer control part 5 optionally varies the center position of a buffer 1. A buffer storage quantity variation monitor part 4 monitors the variation quantity of data stored in the buffer 1 according to a period T set in a timer 6. The buffer control part 5 shifts the monitored center position of the buffer 1 to an arbitrary position according to the result of the monitoring by the monitor part 4. Further, the monitor part 4 finds a statistical protection buffer from the variation quantity and the buffer control part 5 computes an offset value set to the buffer according to the protection buffer.
Inventors:
Yamada, Toshio
Matsui, Yasuo
Matsui, Yasuo
Application Number:
JP2000352536A
Publication Date:
April 26, 2004
Filing Date:
November 14, 2000
Export Citation:
Assignee:
NEC COMMUN SYST LTD
International Classes:
H04L13/08; H04L7/00; (IPC1-7): H04L7/00; H04L13/08
Attorney, Agent or Firm:
丸山 隆夫
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