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Title:
DIFFERENTIAL AMPLIFICATION CIRCUIT
Document Type and Number:
Japanese Patent JPS63197094
Kind Code:
A
Abstract:

PURPOSE: To obtain a differential amplification circuit whose speed is high and whose power consumption is low by controlling a logic threshold so that an output from one of two pairs of invertor circuits goes to high level and an output from another goes to low level.

CONSTITUTION: When both input voltages V1 and V2 become higher than the logic threshold Vth, the outputs from the invertor circuits 1 and 2 go to low level and the output from a NOR circuit 5 goes to high level, then the output from the NOR circuit 6 goes to low level, so that a control voltage Vc raises and the value Vth of the invertor circuits 1 and 2 raises, as well. When both input voltages V1 and V2 become lower than the value Vth, the value Vth goes to low because of the occurrence of inverse voltage change. When one of the input voltages V1 and V2 becomes higher than the value Vth and another becomes lower than that, both of outputs from the NOR circuits 5 and 6 go to low level and the control voltage Vc and the logic threshold value Vth go to a fixed value to be stabilized.


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Inventors:
MASUDA NOBORU
MASAKI AKIRA
Application Number:
JP2823987A
Publication Date:
August 15, 1988
Filing Date:
February 12, 1987
Export Citation:
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Assignee:
HITACHI LTD
International Classes:
G11C11/409; G11C11/34; H01L21/8242; H01L27/10; H01L27/108; H03F3/45; H03K5/02; (IPC1-7): G11C11/34; H01L27/10; H03F3/45; H03K5/02
Attorney, Agent or Firm:
Katsuo Ogawa



 
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