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Patent Searching and Data


Title:
DIFFERENTIAL AMPLIFIER CIRCUIT
Document Type and Number:
Japanese Patent JPH11272786
Kind Code:
A
Abstract:

To set an offset voltage at an optional value without deteriorating a characteristic even in an input voltage near GND by adding a drain grounding circuit consisting of a constant current source capable of varying a current through trimming and of an enhancement type P-MOS transistor to the respec tive input of a differential amplifier circuit.

This circuit is constituted of a differential pair 100 composed of enhancement type P-MOS transistors 102 and 103 and a current mirror circuit 101 composed of enhancement type P-MOS transistors 104 and 105. Further, drain grounding circuits 107 and 108 consisting of constant current sources 109 and 110 capable of varying a current by trimming utilizing a laser or the like and of enhancement type P-MOS transistors 102 and 103 for level shifting are added. The enhancement type P-MOS transistor 102 or 103 of the differential pair 100 is not turned to an unsaturated state.


Inventors:
FUKUI ATSUO
Application Number:
JP7807098A
Publication Date:
October 08, 1999
Filing Date:
March 25, 1998
Export Citation:
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Assignee:
SEIKO INSTR INC
International Classes:
G06G7/163; H01L21/822; H01L27/04; H03F3/34; H03F3/45; (IPC1-7): G06G7/163; H01L21/822; H01L27/04; H03F3/34; H03F3/45
Attorney, Agent or Firm:
Keinosuke Hayashi