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Title:
DIFUSING METHOD OF IMPURITY INTO SEMICONDUCTOR LAYER
Document Type and Number:
Japanese Patent JPH06216057
Kind Code:
A
Abstract:

PURPOSE: To enable the diffusion depth of impurity to be enhanced in accuracy and monitored through a non-destructive manner when impurities are diffused into a semiconductor from a solid diffusion source.

CONSTITUTION: A device is composed of a semiconductor wafer where at least two epitaxial layers 2 and 3 or more layers of different materials or different from each other in carrier concentration are formed, a solid diffusion source 6 formed on the wafer, and a metal electrode 20 provided onto the solid diffusion source 6, wherein a measuring circuit equipped with a bias voltage applying system 31 which applies a bias voltage between the metal electrode 2 and a semiconductor substrate and a diffusion depth measuring system 32 which is able to measure a capacitance between them is provided, so that impurities can be diffused measuring a capacitance between a metal electrode and a semiconductor substrate. By this setup, the diffusion depth of impurities can be monitored through a non-destructive method while a impurity diffusing process is carried out, so that impurity diffusion can be enhanced in controllability, and a wafer is protected against damage, and consequently an impurity diffusion process can be automated.


Inventors:
HIRONAKA MISAO
Application Number:
JP716893A
Publication Date:
August 05, 1994
Filing Date:
January 20, 1993
Export Citation:
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Assignee:
MITSUBISHI ELECTRIC CORP
International Classes:
H01L21/22; H01L21/66; (IPC1-7): H01L21/22; H01L21/66
Attorney, Agent or Firm:
Kenichi Hayase



 
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