PURPOSE: To evade the missing of a parallel data by transferring a data stored in the 1st storage means to the 2nd storage means only after the data stored in the 2nd storage means is read out.

CONSTITUTION: RS-FFs 133, 134 and a 4-input AND gate 135 are added. The RS-FF 133 is provided corresponding to the 1st D-FF 111∼11N. Thus, a ready signal indicating the possibility to enter a new serial data to the 2nd D-FF 111∼11N for the parallel processing is outputted from a ready signal output terminal 143. On the other hand, the RS-FF 134 is provided corresponding to the 2nd D-FFs 121∼12N. Thus, a full signal indicating the possibility to read out a new parallel processing data is outputted from a full signal output terminal 162. Furthermore, the output of an AND gate 135 is fed to a clock terminal CK of the D-FFs 121∼12N.