PURPOSE: To satisfactorily detect digital data by a low-speed circuit by dividing input digital data to data of an even string and data of an odd string to perform the arithmetic processing and performing viterbi decoding thereafter.
CONSTITUTION: Binary digital data is detected from the signal, which is reproduced from a video tape 1 by a magnetic head 2, by an A/D converter 6 in accordance with the reproduced signal level based on the reproducing clock supplied from a PLL circuit 7. This data is divided to data of the even string and data of the odd string, and arithmetic processing of (1+D) is performed in arithmetic processing circuits 21 and 22 by these data of the even string and the odd string, and viterbi decoding is individually performed by viterbi decoding circuits 23 and 24, and outputs of the odd system and the even system are alternately switched and are mixed into data of one system, and it is supplied to an output terminal 26. Thus, a detector has the simple circuit constitution operated with the clock having a relatively low frequency.
| JPS5943860 | [Title of the Invention] Frame synchronization signal detector circuit |
| JPS63222373 | INFORMATION READER |
| JPH05189884 | DATA SYNCHRONIZING SYSTEM |
SEKI TAKAHITO
KANOTA KEIJI
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