PURPOSE: To specify a sampling time by an A/D conversion time and a storage time and to obtain high quality by reading a digital signal being a delay output from a storage means on the way of applying A/D conversion to an analog signal, and storing the digital signal subject to digital conversion to the storage means after A/D conversion.

CONSTITUTION: A low pass filter 10 limits the band of an analog signal supplied to an input terminal 12 to a half of the sampling frequency in the case of A/D conversion by an A/D converter 14. The digital signal from the A/D converter 14 is stored in a shift register 16 of 16-stage configuration one by one bit each and the storage value of each stage is stored in a dynamic memory 18. The stored digital signal is read and converted into an analog signal by a D/A converter 20, fed to relevant sample-and-hold circuits 22a-22c and fed to delay output terminals 26a-26c via low pass filters 24a-24c. Thus, one sampling time is specified by A/D conversion time + write time to storage means and a high quality circuit is attained.