PURPOSE: To enlarge an applied range with simple configuration by providing a multiplier for the high-order bit of a coefficient, delay element and signal switching means for switching the connection of them, and providing an output signal for which the main part of the coefficient is calculated by the multiplier for high-order bit corresponding to the selection of the signal selecting means.

CONSTITUTION: For example, the coefficient to be dealt with the low-order coefficient of 6 bits is set to multipliers ML1-MLn for low-order bit and when it can not be dealt with by the multiplier for 6 bits, the high-order coefficient is set to multipliers MH1-MHm for high-order bit and connected with a desired tap. When a number (n) of taps is 512 and a number (m) of multipliers for high-order bit is 64, concerning digit matching at an adder A, a final step output (a) of an adder for high-order bit is 19 bits adding 6 bits corresponding to the number of multipliers for high-order bit to 8 bits + 5 bits =13 bits outputted from the multiplier for high-order bit and a final step output (b) of an adder for low-order bit is 23 bits adding 9 bits to the 8 bits + 6 bits = 14 bits but a filter output C is 24 bits finally.