Title:
DIGITAL SIGNAL NOISE ELIMINATING CIRCUIT
Document Type and Number:
Japanese Patent JPS62220017
Kind Code:
A
Abstract:
PURPOSE: To eliminate a noise in a digital signal by regarding the noise and setting the threshold level of a counter to the number of rectangular clock signals corresponding to said prescribed time.
CONSTITUTION: A pulse circuit 1 inputs a digital signal 20, and when the signal 20 changes from 0 to 1 or vice versa, the circuit 1 outputs a pulse signal being a reset signal 30 of the counter 3. Then the threshold level of the counter 3 is set to the number of clock rectangular wave signals 10 corresponding to the said prescribed time. Then the digital signal shorter than the prescribed time is interrupted by an FF circuit 4 and only the digital signal 20 longer than the time passes through and is outputted to an output line.
Inventors:
ITO HIDENORI
Application Number:
JP6310186A
Publication Date:
September 28, 1987
Filing Date:
March 20, 1986
Export Citation:
Assignee:
MIYAGI NIPPON DENKI KK
International Classes:
H03K5/1252; H03K5/00; (IPC1-7): H03K5/00
Attorney, Agent or Firm:
Ozeki Shinsuke
Previous Patent: CLOCK BOTH PHASES DRIVE FF CIRCUIT WITH SET OR RESET
Next Patent: TIME REPRODUCING CIRCUIT DEVICE OF WIDE BAND DIGITAL SIGNAL
Next Patent: TIME REPRODUCING CIRCUIT DEVICE OF WIDE BAND DIGITAL SIGNAL