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Title:
DIGITAL SIGNAL PROCESSOR
Document Type and Number:
Japanese Patent JPH03214806
Kind Code:
A
Abstract:

PURPOSE: To simplify the programming processing a delay data in the case of generating a reflecting sound by providing an address control device setting the address space of an external delay RAM for storing the result of calculation independently of L and R channels.

CONSTITUTION: In an external delay RAM for storing the result of calculation, an L channel write address register 102 fixes '1' to the MSB to allocate a high-order address space of the RAM and an R channel write address register 109 fixes '0' to the LSB to allocate a low-order address space of the RAM. As for the control of each channel, the L and R channels are selected by a data multiplexer 105, an address is outputted from a data bus 107 and the transmission reception of the data is implemented by a data bus 115. Thus, the delay in the L and R channels is independently controlled.


Inventors:
MATSUMOTO YOICHI
Application Number:
JP966890A
Publication Date:
September 20, 1991
Filing Date:
January 19, 1990
Export Citation:
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Assignee:
NEC CORP
International Classes:
H03H17/02; G06F17/10; H03H17/06; (IPC1-7): G06F15/31; H03H17/06
Attorney, Agent or Firm:
Uchihara Shin



 
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