Title:
DINAMIC LOGIC ARRAY
Document Type and Number:
Japanese Patent JPH01218212
Kind Code:
A
Abstract:
PURPOSE: To provide a logic array which is operable only through two stages and accelerates its operating speed by providing 1st and 2nd logic gate matrixes and a precharge means for these logic gates. CONSTITUTION: When an input signal E is impressed between precharge(Pch) stages PH0 of a 1st matrix(Mtx), an output line S of a 2nd Mtx 2 is Pch-ed to a prescribed voltage value by a Pch circuit 5. Then, a 1st separating means 8 turns an output line ME of the Mtx 1 to the state of communicating with the input of a storage means 7 and finally turns a Pch circuit 3 and a voltage force circuit 4 into inhibited state. As a result, the Mtx 1 assumed first Pch-ed is made active during the stage PH0. On the next stage PH1, the Pch circuit 3 and the voltage force circuit 4 at the Mtx 1 are made active, and a 2nd separating means 9 transmits the signal stored in the means 7 on the preceding stage toward the input of the Mtx 2. When the circuit of the Mtx 2 is stabilized, a signal expressing a logic function provided by the logic array appears on the output line S.
Inventors:
FURANSUWA ANSOO
Application Number:
JP3067088A
Publication Date:
August 31, 1989
Filing Date:
February 12, 1988
Export Citation:
Assignee:
BULL SA
International Classes:
H03K19/177; H03K19/096; (IPC1-7): H03K19/096; H03K19/177
Domestic Patent References:
| JPS61101124A | 1986-05-20 | |||
| JPS59125125A | 1984-07-19 |
Attorney, Agent or Firm:
Kyozo Yuasa (6 people outside)
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