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Title:
DIODE
Document Type and Number:
Japanese Patent JPS60100476
Kind Code:
A
Abstract:

PURPOSE: To reduce the power loss by forming the state that one of P type and N type regions is buried in the other type of region, thereby doubling the area of a P-N junction in the same chip area as the conventional one.

CONSTITUTION: The state that one of P type and N type regions is buried in the other type of regions is formed. For example, a shallow N type layer 2b is formed upside of a P type layer 2, and the layer 2 is buried in N type layers 1, 2a, 2b. In such a diode, only the bottom of the P type layers is bonded with the N type layer as the conventional one, but the entire layer 2 is buried in the N type layers 1, 2a, 2b so that the entire layer 2 is bonded to the N type layer. Accordingly, the area of the P-N junction can be doubled in the same chip area as the conventional one, thereby reducing by half the resistance component of the forward characteristic of the diode to reduce the power loss.


Inventors:
IITAKA YUKIO
Application Number:
JP20781283A
Publication Date:
June 04, 1985
Filing Date:
November 05, 1983
Export Citation:
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Assignee:
MATSUSHITA ELECTRIC WORKS LTD
International Classes:
H01L29/861; (IPC1-7): H01L29/91
Attorney, Agent or Firm:
Takehiko Matsumoto



 
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