DISPLAY CONTROLLER

Japanese Patent JP3307750

B2

PURPOSE: To stably generate a displaying clock signal corresponding to the fluctuation in a frequency of a reference signal by gradually multiplying the displaying clock signal, comparing it with the reference signal and generating a clock signal based on the comparison result.
CONSTITUTION: A frequency divider 24 gradually multiplies the displaying clock signal fOUT according to a gradual multiplication value stored in a frequency division value register 25 to generate a gradual multiplication signal fV. A phase comparator 21 detects the frequencies and a phase difference of a horizontal synchronizing signal HD inputted from a computer equipment and the gradual multiplication signal fV, and generates a mean DC voltage in proportion to the error, and applies it to a control terminal of a voltage controlled oscillator(VCO) through a low band filter 22. The VCO 23 generates the displaying clock signal fOUT based on the inputted DC voltage. Thus, even when the reference signal (horizontal synchronizing signal HD) is outputted at plural frequencies, a required (according to the value of the frequency division value register 25) gradually multiplied frequency signal is obtained stably from the VCO 23 corresponding to the fluctuation in the frequency.

JP2745869	VARIABLE CLOCK FREQUENCY DIVIDING CIRCUIT
JPH07141054	CLOCK FREQUENCY VARYING SYSTEM

Takashi Tsunoda
Yuichi Takagi

JP33737893A

July 24, 2002

December 28, 1993

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キヤノン株式会社
ソニー株式会社

G06F1/08; G09G3/20; G09G5/00; G09G5/18; G09G5/36; H03L7/183; H04N5/04; (IPC1-7): G09G5/18; G06F1/08; H03L7/183; H04N5/04

JP6314088A
JP514760A
JP4266221A
JP24363U

Yasunori Otsuka (1 person outside)

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