PURPOSE: To prepare a carry-out signal for a rounding processing at a high speed.

CONSTITUTION: A divider circuit which searches the final quotient of the mantissa of a floating point division by repeatedly searching plural partial quotients constituted of plural bits, is provided with a detection circuit 5 which detects that the plural bits of each of the partial quotients are all '1', a register 6 which holds the detected result obtained by the detection circuit 5, and a discrimination circuit 7 which outputs a carry-in signal according to a round mode signal, based on the finally searched partial quotient among the repeatedly searched plural partial quotients and the output of the register 6. Then, the carry-in signal is inputted to a round circuit 4 which operates the rounding processing, and an adder circuit 8 which computes an excomponent part.