PURPOSE: To enable high-speed transferring without completely stopping CPU, corresponding to a wide-range transfer request of a DMA device.

CONSTITUTION: A DMA controller 102 obtains the usage right of busses 105, 106 and 107 at the time of a DMA request and starts transferring. In this case, a transfer interval timer 211 is started, transfer is interrupted when the prescribed time elapses and returns control to CPU. During transfer, transferred data quantity is counted by a temporary counter 210. Transfer speed is calculated by data quantity and passage time, time according to the transfer speed is set in the timer 211 again and succeeding transfer is executed. Thus, since control is returned to CPU at every prescribed time, a system where a processing by CPU is not completely stopped without slowing down DMA speed more than necessity is constituted.