PURPOSE: To easily identify an input/output control part to have caused DMA time-over, and to contrive high speed in coping with the fault processing by monitoring the condition of a DMA requiring signal outputted from each input/ output control part.

CONSTITUTION: A bus use permitting signal is outputted from a bus control part 103, and whenever a corresponding input/output control part 101 requires a data transfer by means of a DMA (direct memory access) control, the condition of the DMA requiring signal at such a time outputted from each input/ output control part 101 is latched by a holding means 111. Further, the newest conditions are successively held until the DMA time-over is generated. Consequently, when a DMA error signal due to the DMA time-over is inputted to a central processing part 105, a read control means 113 reads holding information from the holding means 111. Thus, the input/output control part 101 to which a bus using right is added can be identified, and in which output control part 101 the DMA time-over is generated can be recognized.