PURPOSE: To detect the abnormality of DMA transfer by comparing a sum check code prepared by means of a sum check preparing circuit at the time of transfer with a sum check code stored in a buffer memory in a transfer destination.

CONSTITUTION: Data (1)-data (n) stored in a buffer memory 20 are transferred again to a system-side memory 11 by a DMA controller 22. At the same time, data (1)-data (n) are loaded on the sum check generation circuit 12 and the sum check code is prepared. When the controller 22 completes the transfer of data (1)-data (n), CPU 10 checks whether DMA transfer is normally executed or not. Namely, data (1)-data (n) loaded on the circuit 12 are loaded on an operation register ACC 14, data (1)-data (n) stored in the memory 20 are loaded on a register B13, and both data are compared. The normal termination and abnormality of DMA transfer is decided by coincidence/noncoincidence.