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Patent Searching and Data


Title:
DOUBLE BALANCED FREQUENCY MULTIPLIER
Document Type and Number:
Japanese Patent JPS62210706
Kind Code:
A
Abstract:

PURPOSE: To increase the maximum frequency limit and to widen the frequency characteristic by flowing a current of the unbalanced mode at the outer side of a balun and a current of the balanced mode at the inner side.

CONSTITUTION: Main lines 4a, 5a are formed on a dielectric board 11 by a metallic conductor layer and an input terminal 1 and an output terminal 2 are provided at the center of the outer ridge. The input/output terminals 1, 2 are connected to ground potential. A couple of sub lines 4b, 4c and 5b, 5c are formed vertically in opposite to the main lines 4a, 5a. Then a through hole 4d is provided to the inner side of the main line 4a via the board 11 from the inner edge of the sub line 4b, the sub line 4b and the main line 4a are connected and the connection above is similar in the connection between the sub line 5b and the main line 5a. A bridge circuit comprising diodes 6a∼6d is connected between the baluns 4, 5 constituted in this way. Thus, a current of the unbalanced mode flows between each outer edge of the baluns 4, 5 and the ground conductor and electric fields of the same amplitude but opposite phase are produced at each inner side. Thus, the broad band characteristic is obtained and the multiplier is used even at a high frequency region.


Inventors:
IZUMI ISAO
Application Number:
JP5567986A
Publication Date:
September 16, 1987
Filing Date:
March 12, 1986
Export Citation:
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Assignee:
NEC CORP
International Classes:
H03B19/05; (IPC1-7): H03B19/05
Attorney, Agent or Firm:
Uchihara Shin