Title:
TIME COUNTING SYNCHRONIZATION METHOD AND TIME COUNTING SYNCHRONIZATION CIRCUIT
Document Type and Number:
Japanese Patent JP3246459
Kind Code:
B2
Abstract:
PROBLEM TO BE SOLVED: To realize high time counting accuracy by synchronizing in a short time with a low frequency signal from a high accuracy clock such as 1 second pulse signal obtained from a GPS receiver.
SOLUTION: For synchronizing with a high accuracy clock 1 having a low frequency output, PLL circuits 21, 22, 23, 24, 25 and 26 having added a circuit 20 controlling a frequency dividing ratio are used. When the time difference between the output of the high accuracy clock 1 and the output of the frequency divider 26 exceeds a certain time, an AND circuit 203 detects it, switches a selector 204, increases the frequency dividing ratio for a certain period, quickly decreases the phase shift between the output of the high accuracy clock 1 and the output of the frequency dividing circuit and shortens time necessary for synchronizing.
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Inventors:
Tatsuaki Matsumoto
Application Number:
JP35351598A
Publication Date:
January 15, 2002
Filing Date:
December 11, 1998
Export Citation:
Assignee:
NEC
International Classes:
G04R20/00; G01V1/28; G04C9/04; H03K19/0175; H03L7/08; (IPC1-7): G04G7/02; H03L7/08
Domestic Patent References:
| JP62108184A | ||||
| JP9284680A | ||||
| JP8274673A | ||||
| JP10148678A | ||||
| JP2265324A | ||||
| JP60145728A |
Attorney, Agent or Firm:
Yasuo Suzuki (1 person outside)