Title:
二重ゲート電界効果トランジスタのゲート信号印加方法
Document Type and Number:
Japanese Patent JP4257971
Kind Code:
B2
Abstract:
In an insulated double gate FET, the threshold voltage during the operation of a transient response thereof is enabled to be arbitrarily and accurately controlled by a method that includes applying a first input signal intended to perform an ordinary logic operation to one of the gate electrodes thereof and applying, in response to this signal, a second signal that has a signal-level temporal-change direction as the first input signal and has at least one of the low level and the high level thereof shifted by a predetermined magnitude or endowed with a predetermined time difference or has the time slower or faster signal level change of the signal to the other gate electrode.
Inventors:
Toshihiro Sekikawa
Kohei Hohei
Nakagawa
Kohei Hohei
Nakagawa
Application Number:
JP2003087386A
Publication Date:
April 30, 2009
Filing Date:
March 27, 2003
Export Citation:
Assignee:
National Institute of Advanced Industrial Science and Technology
International Classes:
H01L21/822; H01L29/786; G06G7/18; H01L27/04; H03K3/356; H03K17/30
Domestic Patent References:
| JP2001284592A |