PURPOSE: To enable to markedly reduce the size of a chip, by a method wherein a high voltage from a boosting circuit connected to a low voltage source is supplied to a CMOS level shifting circuit to drive an output transistor.
CONSTITUTION: A voltage of 5V from the low voltage source 3 is impressed on a logical circuit 4 in a low voltage system and the boosting circuit 7, and a digital controlling signal from the circuit 4 is fed to an inverter IN and an N type MOS transistor N-TR1. In response to the output from the circuit 4, impressing of a high voltage on the output transistor 61 from the circuit 7 is controlled, whereby passing of an electric current to a heating element 21 is controlled. Since each level-shifting circuit 51...consists of a CMOS circuit, it consumes little electric power. Accordingly, the output impedance of the boosting circuit 7 may be high, the circuit 7 may be constructed on a small scale, the channel width of each output transistor 61 can be reduced, and the size of the chip can be reduced.
NISHIO HARUHIKO
MATSUURA YOSHIAKI
| JPS50118629A | 1975-09-17 |