Title:
DUAL PORT MEMORY
Document Type and Number:
Japanese Patent JP2500740
Kind Code:
B2
Abstract:
PURPOSE: To reduce the number of circuit elements and a chip area holding high speed operation.
CONSTITUTION: Bit lines of one word line of each memory cell array section 11-1n are divided into (k) groups having (m) lines respectively, and data buses DB1-DBk of (k) lines being in common to these memory cell array section are provided. Bit selection circuits 41-4n which perform selective data transfer between these data bus DB1-DBk and the memory cell array sections 11-1n are provided. Also, a shift register circuit in which the data buses DB1-DBk and partial shift register 51-5m having corresponding registers (R11-R1k etc.) respectively are cascaded, parallel data transfer is performed for each partial shift register between the data buses DB1-DBk and the above mentioned circuit, and inputting and outputting serial data are performed between one of the partial shift registers and an external circuit is provided.
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Inventors:
AIMOTO YOSHIHARU
SUGIBAYASHI NAOHIKO
SUGIBAYASHI NAOHIKO
Application Number:
JP7843393A
Publication Date:
May 29, 1996
Filing Date:
April 06, 1993
Export Citation:
Assignee:
NIPPON ELECTRIC CO
International Classes:
G11C11/41; G11C7/00; G11C7/10; G11C11/401; (IPC1-7): G11C11/401; G11C7/00
Domestic Patent References:
| JP4219691A | ||||
| JP5159567A |
Attorney, Agent or Firm:
Naoki Kyomoto (2 outside)