PURPOSE: To reduce current consumption at the time of refresh cycle by operating only a part connected to a memory cell requiring refresh among split bit line pairs at the time of refresh cycle.

CONSTITUTION: When the falling of the inverse of a signal CAS is faster than the falling of the inverse of a signal RAS, the refresh mode is started and an internal signal REF reachs a H level. In this case, not an external input address RA8 but an address Qi (i=0W8) of a refresh address counter provided in the inside is latched at the falling of the inverse of signal RAS and memory cell data of a corresponding row address is refreshed. In case of Q8=0 at the refresh cycle as above, for example, a memory cell array block #1 is operated, but signals r and s2 remain on a L level. Thus, the memory cell array block #2 is inoperative and bit line pairs BL0, and the inverse of BL0 keep the precharge state.