Title:
DYNAMIC VOLTAGE INTEGRATING METHOD AND CIRCUIT FOR EXECUTING AND APPLYING THE SAME
Document Type and Number:
Japanese Patent JP3084097
Kind Code:
B2
Abstract:
PURPOSE: To provide a voltage integrating method with small electric energy consumption and a circuit used for this method.
CONSTITUTION: This circuit is an integration one being a pair of bipolar transistors or CMOS transistors T5 and T6 in which an active element controls the storage of sample charge from a signal voltage (Us) to a sampling capacitor (Ci), and the discharge of the sample to an integrating capacitor (Co) by a switch. This circuit consumes currents only while the charge is moved.
Inventors:
Yuha La Pelli
Application Number:
JP21868991A
Publication Date:
September 04, 2000
Filing Date:
August 29, 1991
Export Citation:
Assignee:
Nokia Mobile Phones Limited
International Classes:
G01R19/00; G06G7/184; (IPC1-7): G06G7/184; G01R19/00
Domestic Patent References:
| JP60140478A | ||||
| JP57123717A |
Attorney, Agent or Firm:
Sota Asahina (2 outside)
Previous Patent: 自転軸を廃止し自在回転を可能にした、地球儀
Next Patent: SYSTEM AND DEVICE FOR INTERACTIVE PROCESSING OF COMPUTER ANIMATION
Next Patent: SYSTEM AND DEVICE FOR INTERACTIVE PROCESSING OF COMPUTER ANIMATION