PURPOSE: To obtain fast and stable solution in a numeric analysis of the semiconductor element.
CONSTITUTION: This device is equipped with an input part 12, a time step setting part 14, a calculation part 15 for a decoupled method, and a calculation part 16 for a Newton method, and has a switching part 17 for switching the two calculation parts. The decoupled method calculation part 15 and Newton method calculation part 16 are properly switched by the switching part 17 and an energy conservation law of electron and an energy conservation law of positive hole are solved in addition to a Poisson's equation, an electron current continuous equation, and a positive hole current continuous equation to calculate electron temperature and positive hole temperature in addition to a potential, electron density, and positive hole density. Further, the input part 12 is so constituted as to handle the semiconductor element having three-dimensional structure in a two-dimensional area and the time step setting part 14 sets an optimum time step.
JP2002202890 | AUTHORING TOOL FOR BAYESIAN NETWORK DIAGNOSING SYSTEM |
JPS57202556 | FAULT DIAGNOSIS CONTROLLER |
JPH04205436 | LOGIC CIRCUIT |
Next Patent: DIGITAL PATTERN DISCRIMINATING VECTOR PROCESSOR