Title:
電気コンポーネントの製造方法および電気コンポーネント構造
Document Type and Number:
Japanese Patent JP5296303
Kind Code:
B2
Abstract:
A self-aligned, thin-film, top-gate transistor and method of manufacturing same are disclosed. A first print-patterned mask is formed (108) over a metal layer by digital lithography, for example by printing with a phase change material using a droplet ejector. The metal layer is then etched (110) using the first print-patterned mask to form source and drain electrodes. A semiconductive layer and an insulative layer are formed (114) thereover. A layer of photosensitive material (118) is then deposited and exposed (120) through the substrate, with the source and drain electrodes acting as masks for the exposure. Following development (122) of the photosensitive material, a gate metal layer is deposited (124). A second print-patterned mask is then formed (126) over the device, again by digital lithography, Etching (128) and removal (132) of the photosensitive material leaves the self-aligned top-gate electrode.
Inventors:
William s won
Rene Alehan
Eugene M Chu
Rene Alehan
Eugene M Chu
Application Number:
JP2006201598A
Publication Date:
September 25, 2013
Filing Date:
July 25, 2006
Export Citation:
Assignee:
Palo Alto Research Center Incorporated
International Classes:
H01L21/336; H01L21/28; H01L21/3213; H01L21/768; H01L29/417; H01L29/786
Domestic Patent References:
| JP62030376A | ||||
| JP61078166A | ||||
| JP2004096082A |
Attorney, Agent or Firm:
Kenji Yoshida
Jun Ishida
Jun Ishida