Title:
電子回路
Document Type and Number:
Japanese Patent JP4002378
Kind Code:
B2
Abstract:
A dummy wiring 25 is provided for simulating an actual wiring 26 connecting semiconductor integrated circuits 2 and 6 on a circuit board. The semiconductor integrated circuit comprises a data output circuit 28 capable of variably setting the slew rate and a circuit 29 for measuring signal delay time between a signal sending point and a signal reflection point (characteristic impedance mismatching point) using the dummy wiring 25, and the delay time so obtained by the measuring circuit is used for the determination of the signal transition time of the output circuit. The transition time of the signal is set at least twice of the signal delay time between the signal sending point and the wiring branch at the nearest end. In this way, signal transmission with alleviated reflection by the reflection point at the nearest end is realized.
Inventors:
Seiji Senba
Yoji Nishio
Yoji Nishio
Application Number:
JP36879499A
Publication Date:
October 31, 2007
Filing Date:
December 27, 1999
Export Citation:
Assignee:
Elpida Memory Co., Ltd.
International Classes:
G06F12/00; G01R31/28; G06F13/16; G11C5/00; G11C7/10; G11C7/22; G11C11/401; G11C11/4076; G11C29/02; H01L21/822; H01L27/04; H03K19/0175; H05K1/02; H05K1/14
Domestic Patent References:
| JP7226666A | ||||
| JP6112780A | ||||
| JP5057931U | ||||
| JP3272167A | ||||
| JP3227112A | ||||
| JP2122725A | ||||
| JP7106943A | ||||
| JP4170049A | ||||
| JP9089991A | ||||
| JP5322981A |
Attorney, Agent or Firm:
Akio Miyazaki
Ishibashi Masayuki
Masaaki Ogata
Ishibashi Masayuki
Masaaki Ogata