Title:
EMULATION METHOD AND EMULATOR DEVICE FOR MICROPROCESSOR
Document Type and Number:
Japanese Patent JP3685288
Kind Code:
B2
Abstract:
PROBLEM TO BE SOLVED: To make efficiently debuggable a program, to reduce the developing procedure for the program and to improve the development efficiency, by interrupting emulation after an interruption process was executed, transferring the values of registers and a program counter and memory data at the time of the interrupting, and performing simulation.
SOLUTION: An emulation controller 6 executes emulation and is equipped with various debugging functions, and when an emulation CPU 1 executes an interruption program, the end of the execution is detected to interrupt the emulation. To predict a process prior to the execution of emulation as a following process, a simulator 10 is actuated, the values of the registers of the emulation CPU 1, the value of the program counter, and memory data at the time of the interruption of the simulation are transferred to the simulator 10, which is used to perform emulation for predicting a process in advance.
Inventors:
Kazuhiro Inaoka
Application Number:
JP15127897A
Publication Date:
August 17, 2005
Filing Date:
June 09, 1997
Export Citation:
Assignee:
Renesas Technology Corp.
Renesas Solutions Corporation
Renesas Solutions Corporation
International Classes:
G06F11/28; G06F11/22; (IPC1-7): G06F11/22; G06F11/28
Domestic Patent References:
| JP57089157A | ||||
| JP1036344A |
Attorney, Agent or Firm:
Hiroaki Tazawa
Konobu Kato
Hideaki Tazawa
Hamada Hatsune
Konobu Kato
Hideaki Tazawa
Hamada Hatsune
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