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Title:
ENVELOPE FOR HIGH-FREQUENCY SEMICONDUCTOR
Document Type and Number:
Japanese Patent JPS63174342
Kind Code:
A
Abstract:

PURPOSE: To simplify construction and to lower the manufacture cost thereof, by providing a high-frequency FET chip so as to be received in an envelope and forming a bypassing capacitor of ceramics, the capacitor being connected to a common terminal of the transistor.

CONSTITUTION: A dielectric insulator 2 is secured on a radiator 1 of copper or the like by means of silver solder or the like. The insulator 2 has a hole 2' at the center thereof so that an FET chip 3 is to be mounted on the radiator 1 within the hole 2'. An electrode pattern 4 for providing one of the electrodes of a bypassing capacitor is formed by metallization on the periphery of the hole 2' on the top of the insulator 2. A metallized section 6 is formed on the top of the insulator 2 for securing an FET lead terminal 5, while a metallized section 8 is formed in connection with the electrode pattern 4 for securing a lead terminal 7 for connecting a source resistance.


Inventors:
KIKUCHI TOSHIRO
Application Number:
JP510787A
Publication Date:
July 18, 1988
Filing Date:
January 14, 1987
Export Citation:
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Assignee:
TOSHIBA CORP
International Classes:
H01L23/12; H03F3/60; (IPC1-7): H01L23/12; H03F3/60
Attorney, Agent or Firm:
Takehiko Suzue



 
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