Title:
EPITAXIAL CHANNEL MOS TRANSISTOR AND MANUFACTURING METHOD THEREOF
Document Type and Number:
Japanese Patent JP2780670
Kind Code:
B2
Abstract:
PURPOSE: To enhance the subthreshold characteristics while simplifying the manufacturing steps by a method wherein the impurity distribution is specified so that the impurity concentration in the channel part may be lower in the gate oxide film interface, to be high concentration in the medium depth part while low connection in the deepest part.
CONSTITUTION: The impurity concentration in a channel part is lower on the gate oxide film interface becoming a thin high concentration layers in the medium depth while becoming low concentration again in the deepest part. At this time, in case of off time of the channel part, a depletion layer 28 reaches a low concentration layer 24 but most of the depletion layer 28 remains in low concentration layer 28 and the high concentration 25. Since the depletion layer 28 extending from source drain is blocked by the high concentration layer 25, punch through is suppressed. Finally, when the gate voltage is boosted to supply the threshold voltage, the concentration of the low concentration layer 24 is set up to be extremely low level so that the depletion layer 28 may be notably expanded into the low concentration layer 24.
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Inventors:
Akira Tanabe
Application Number:
JP11360195A
Publication Date:
July 30, 1998
Filing Date:
April 14, 1995
Export Citation:
Assignee:
NEC
International Classes:
H01L29/78; H01L21/31; H01L21/8238; H01L27/092; (IPC1-7): H01L29/78; H01L21/31; H01L21/8238; H01L27/092
Domestic Patent References:
| JP5961070A | ||||
| JP52116179A |
Attorney, Agent or Firm:
Asato Kato