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Title:
EQUIPMENT AND METHOD OF ALIGNING SEMICONDUCTOR WAFER
Document Type and Number:
Japanese Patent JPH07335724
Kind Code:
A
Abstract:

PURPOSE: To facilitate an alignment to an orientation flat reference while inhibiting particles generated at the time of alignment, and to improve productivity.

CONSTITUTION: A wafer aligner consists of a wafer-holder and an alignment mechanism section, and a region near the lowermost point of wafers inserted in parallel with the holder is abutted against two rollers disposed at the corresponding places of the alignment mechanism section and the wafers are aligned to an orientation flat reference by the vertical movement and rotation of the rollers in the wafer aligner. The two rollers arranged in parallel at a pitch exceeding no orientation flat length of the semiconductor wafers 11 and capable of being vertically moved independently under the state, in which the parallelism is kept, are formed of a first roller 221 composed of a rubbery elastic material having rubber hardness, by which the wafers 11 can be tuned without slippage by revolution at a time when the wafers 11 are pushed up by abutting in the peripheries of the wafers 11, and a second roller 15 made up of a rubbery elastic material having rubber hardness, by which frictional force smaller than at least frictional force is acquired.


Inventors:
KAWAGUCHI HITOSHI
Application Number:
JP12908394A
Publication Date:
December 22, 1995
Filing Date:
June 10, 1994
Export Citation:
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Assignee:
FUJITSU LTD
International Classes:
B65G49/07; H01L21/68; (IPC1-7): H01L21/68; B65G49/07
Attorney, Agent or Firm:
Teiichi