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Title:
ERROR CHECK BIT TRANSFER SYSTEM
Document Type and Number:
Japanese Patent JPH04252532
Kind Code:
A
Abstract:

PURPOSE: To surely detect an error in a transfer data and to transfer the data at a high speed by utilizing an error check bit.

CONSTITUTION: A sender side is provided with an error check bit generator 1002, an error check bit 1003 is generated from a transmission data 1004 and an error check bit 1003 is sent with a delay from the transmission of a data 1004 by a time required for generating the error check bit. A receiver side uses an error check bit generator 1103 to generate the error check bit 1104 from the reception data 1004, compares the error check bit 1104 and the error check bit 1103 sent from the sender to detect an error in the reception data 1104. The transfer time of the data is independent of the generating time of the error check bit and high speed data transfer having an error check function is attained. The procedure is implemented between in-network exchanges and between an exchange 1200 and a receiver 1300.


Inventors:
KANO TAKESHI
Application Number:
JP2802091A
Publication Date:
September 08, 1992
Filing Date:
January 28, 1991
Export Citation:
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Assignee:
NEC CORP
International Classes:
H04L1/00; H04L12/66; (IPC1-7): H04L1/00; H04L12/66
Domestic Patent References:
JPS63108828A1988-05-13
Attorney, Agent or Firm:
Masatake Shiga



 
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