Title:
ERROR CORRECTING AND DETECTING CIRCUIT AND SEMICONDUCTOR STORAGE DEVICE
Document Type and Number:
Japanese Patent JP3272903
Kind Code:
B2
Abstract:
PURPOSE: To decrease the circuit scale as much as possible by omitting a delay circuit which is large in occupation rate to the circuit scale.
CONSTITUTION: The error correcting and detecting circuit, equipped with an error position and size calculating circuit 2 which calculates the position and size of an error from inspection data and information data, and an error correcting circuit 3 which outputs information data having the error corrected on the basis of the position and size of the error obtained by the circuit 2, finds the position and size of the error from the information data and inspection data which are inputted in a 1st cycle and outputs the information data having the error corrected according to that same information data as the data in the 1st cycle and is inputted in a 2nd cycle and the calculation results of the position and and size of the error.
Inventors:
Toru Tanzawa
Tomoharu Tanaka
Kazunori Ouchi
Riichiro Shirata
Tomoharu Tanaka
Kazunori Ouchi
Riichiro Shirata
Application Number:
JP8345995A
Publication Date:
April 08, 2002
Filing Date:
March 16, 1995
Export Citation:
Assignee:
Toshiba Corporation
International Classes:
G06F12/16; G06F11/10; H03M13/15; (IPC1-7): G06F12/16; G06F11/10
Domestic Patent References:
| JP613916A | ||||
| JP629865A | ||||
| JP6188750A | ||||
| JP58151657A | ||||
| JP59117000A | ||||
| JP5898898A | ||||
| JP439755A |
Attorney, Agent or Firm:
Takehiko Suzue
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