PURPOSE: To automatically correct the one-bit error of memory data by constituting of plural parity bit adding circuits and plural parity check circuits, adding a parity bit at every number data, and detecting which any one bit of data shows abnormality (inversion).
CONSTITUTION: The parity bit adding circuit 7a adds parity to the bits of the data D0-D2. Similarly, the parity bit adding circuit 7b adds the parity to the bits of the data D3-D5, and the parity bit adding circuit 7c adds it to the bits of the data D0, D3, and D6, and the parity bit adding circuit 7b adds it to the bits of the data D1, D4, and D7. In such constitution, for example, the data in the parity bit adding circuits 7b, 7d become a parity error when the data 4 are inverted. In other works, the fact that which bit of the data is inverted can be detected from the data in four parity bit adding circuits 7a-7d. The detection and correction of an inverted bit are performed by a parity check/data correction circuit 17.
WO/2020/186524 | STORAGE AND CHECKING METHOD AND DEVICE |
WO/2000/041182 | MEMORY ARRAY ORGANIZATION |
JP2545386 | [Title of Invention] Information Recording Device |