Title:
ERROR CORRECTION PROCESSING METHOD
Document Type and Number:
Japanese Patent JP2694794
Kind Code:
B2
Abstract:
PURPOSE: To improve the reliability of error correction by discriminating it to be no error when all codes of a syndrome polynomial are 0, checking a high t-order code when not and discriminating it to be disable correction when the codes are all zero, setting a flag and taking over the processing to a next stage.
CONSTITUTION: An AND 115 of a discrimination circuit in the error correction processing ANDs outputs of NOR circuits 114i and 1140-11415 with respect to input 8-bits of an i-th order (1=1-15) to check all zero of a syndrome code. Furthermore, the method employs an AND 116 ANDing outputs of the NOR circuits 114i and 1140-11415 to check all zero of the syndrome code up to high- order 8-bits. That is, whether or not all codes of a syndrome polynomial are 0 is discriminated and when all zero, it is discriminated to be no error. When not all zero, whether or not a high-order t-th code of the polynomial is zero is discriminated and correction disable is discriminated when 0 and no correction is executed, a flag is set to allow a next stage to take over the processing. Thus, proper countermeasure is applied to data string subjected to erroneous discrimination and erroneous correction and the reliability is more improved.
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Inventors:
Nakamura Masaru
Application Number:
JP8317793A
Publication Date:
December 24, 1997
Filing Date:
April 09, 1993
Export Citation:
Assignee:
NEC
International Classes:
G06F11/10; H03M13/00; (IPC1-7): H03M13/00
Domestic Patent References:
| JP60218926A | ||||
| JP6244740A | ||||
| JP677844A | ||||
| JP3195216A | ||||
| JP3172027A | ||||
| JP62188620A | ||||
| JP641332A | ||||
| JP6369328A |
Attorney, Agent or Firm:
Naoki Kyomoto (2 outside)
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