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Patent Searching and Data


Title:
ERROR JUDGING CIRCUIT AND SHARED MEMORY SYSTEM
Document Type and Number:
Japanese Patent JP2010122828
Kind Code:
A
Abstract:

To execute data assurance while improving utilization efficiency of the area of a main storage memory without increasing the cost of a system, in an error judging circuit and the shared memory system.

An error judging circuit includes an error detection circuit unit which in SmEC-DmED using (k, k-3) Reed-Solomon code with P(x) as a primitive polynomial of m-order in a Galois field GF(2), detects if there is a one-block error, a two-block error or no error with respect to a polynomial expression I(x) of an original code as an object to be protected from an error with respect to data of m-bit block unit, and which detects the position p of the block error from S0p=S1 in the Galois extension field GF(2m).


Inventors:
UKAI MASAKI
Application Number:
JP2008294828A
Publication Date:
June 03, 2010
Filing Date:
November 18, 2008
Export Citation:
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Assignee:
FUJITSU LTD
International Classes:
G06F12/16
Domestic Patent References:
JPH07226687A1995-08-22
JPS61126826A1986-06-14
JP2008242034A2008-10-09
JPH01158828A1989-06-21
JP2008165772A2008-07-17
JPH10255402A1998-09-25
JP2000305861A2000-11-02
Foreign References:
US4637021A1987-01-13
US20040236901A12004-11-25
US4637021A1987-01-13
Other References:
JPN6013037627; 近藤 昌晴 外3名: '磁気ディスク用楕円曲線符号の計算量評価' 電子情報通信学会技術研究報告 Vol.101, No.304, 20010907, pp.37-42
Attorney, Agent or Firm:
Tadahiko Ito
Akinori Yamaguchi