Title:
ERROR NUMERIC VALUE POLYNOMIAL AND ERROR POSITION POLYNOMIAL ARITHMETIC CIRCUIT
Document Type and Number:
Japanese Patent JP2694792
Kind Code:
B2
Abstract:
PURPOSE: To easily attain LSI by simplifying a circuit constitution.
CONSTITUTION: In an initial state, each coefficient of a divisor polynomial is set at multiplying circuits 132-130. On the other hand, the coefficients of dividend polynomial are inputted in the descending order, and the highest-order coefficient of the dividend polynomial is outputted from a register circuit 12. The multiplying circuit 132 multiplies the highest-order coefficient of the divisor polynomial by the reciprocal of the highest-order coefficient of the dividend polynomial, and calculates the highest-order coefficient of quotient polynomial. The multiplying circuits 130 and 131 multiply the highest-order coefficient of the quotient polynomial by each coefficient. EXOR circuits 121 and 122 calculate the exclusive logical sum of the outputs of the multiplying circuits 130 and 131 and the outputs of register circuits 110 and 111 on the input sides, that is, the coefficients of remainder polynomial, and allows register circuits 111 and 112 at the output sides to latch the coefficients. A register circuit 210 receives and latches the outputs of the register circuits 112 and 111 in parallel, and outputs the coefficients of error numeric value polynomial as parallel data.
Inventors:
Nakamura Masaru
Application Number:
JP1131893A
Publication Date:
December 24, 1997
Filing Date:
January 27, 1993
Export Citation:
Assignee:
NEC
International Classes:
G06F11/10; G06F7/72; H03M13/00; H03M13/15; (IPC1-7): H03M13/00
Domestic Patent References:
| JP63167527A |
Attorney, Agent or Firm:
Naoki Kyomoto (2 outside)
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