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Title:
ERROR POSITION DETECTING CIRCUIT
Document Type and Number:
Japanese Patent JPS5965914
Kind Code:
A
Abstract:

PURPOSE: To detect an erroneous position of a data by a simple constitution when an error of one word exists in the data, by providing a circuit for detecting the coincidence of a syndrome output of a circuit, and a means for supplying an output of one multiplier of a syndrome calculating circuit to an input of the other multiplier, on a digital audio disk device.

CONSTITUTION: Data stored in shift registers 1, 2, 3 and 4 are inputted to multipliers 11, 12, 13 and 14 through gate circuits G5WG8, respectively, by gate signals g5Wg8, by which outputs of the multipliers 11, 12, 13 and 14 become (D1+ D2), α3(α3D1+D2), α(αD1+D2) and α2(α2D1+D2), respectively. α denotes a root of a detecting code expression, and D1WD32 denote one word. Thereafter, in the same way, whenever a data is inputted, multiplication is executed, by which a syndrome value is obtained. Subsequently, when a driving signal CE is generated, coincidence of S1, S2, S3 and S4 of the syndrome value is detected by coincidence detecting circuits 15, 16 and 17. That is to say, an erroneous position of a data is derived by repeating the multiplication until coincidence is detected, and counting the number of times of multiplication by a counter 19.


Inventors:
WASHIMI IKUAKI
NAKATANI MASARU
SHIMO HITOSHI
Application Number:
JP17717082A
Publication Date:
April 14, 1984
Filing Date:
October 07, 1982
Export Citation:
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Assignee:
SANYO ELECTRIC CO
TOKYO SANYO ELECTRIC CO
International Classes:
G11B7/00; G11B7/004; G11B20/18; (IPC1-7): G11B5/09; G11B7/00
Domestic Patent References:
JPS5741052A1982-03-06
JPS5592954A1980-07-14
Attorney, Agent or Firm:
Koji Yasutomi (1 person outside)